This invention relates to a semiconductor memory, such as a dynamic RAM, for example.
Conventional semiconductor memories, such as dynamic RAMs, are based on the input multiplexing of the row address and column address, and they necessitate a row address strobe, column address strobe and several other timing signals including write control signals, as is well known in the art.
A computer system generally operates in synchronism with a constant system clock, and data to be read out or written into a storage unit is transferred also in synchronism with the system clock. Accordingly, for a storage unit based on the dynamic RAM, in which several timing signals are produced from the system clock, these timing signals need to be set to meet the prescribed timings even in the worst condition in consideration of the variability in the signal delay time, crosstalk noise, and the like. On this account, conventional semiconductor memories cannot fully exert their inherent performances.